1. Field of the Invention
The present invention relates to multi-chip module (MCM) circuit packages fabricated with dielectric tapes such as low temperature cofired ceramic (LTCC) tape, and more specifically to such circuit structures that are assembled in a three-dimensional stack.
2. Description of the Related Art
MCM packages generally include a dielectric structure consisting of a number of layers of insulating material with electrical circuit elements such as resistors, inductors and capacitor plates formed on their surfaces, and conductive routing patterns interconnecting the various elements. The insulating layers are thermally fused together so that the circuit elements are buried, with vertical interconnects (vias) extending through the insulating layers to interconnect circuit elements on adjacent layers.
One or more IC chips and/or discrete components are mounted to the surface of the dielectric structure and connected to its routing by wire bond, flip-chip or other connection techniques. In a flip-chip configuration, a surface of an IC chip upon which bonding pads are formed faces the dielectric structure, and the bonding pads are connected to mating bonding pads on the structure by electrically conductive "bumps" formed from solder, conductive epoxy or other suitable material.
LTCC tape is a desirable material for fabricating MCM structures. This tape includes a mixture of glass and ceramic fillers or recrystallizable glass which sinters at about 850.degree. C., and exhibits a thermal expansion similar to alumina. The low-temperature processing is compatible with air fired resistors and precious metal thick film conductors such as gold, silver or their alloys. It also allows for the processing of base metals such as copper in a nitrogen or reducing atmosphere. A general treatise on LTCC technology is provided in Vitriol et al., "Development of a Low Temperature Cofired Multi-layer Ceramic Technology", ISHM Proceedings, 1983, pages 593-598. An example of an LTCC circuit package is described in U.S. Pat. No. 4,899,118 to Polinski, Sr., assigned to Hughes Aircraft Company, the assignee of the present invention.
A limitation of the present LTCC MCM technology is in the area occupied by the plural IC chips. It would be highly desirable to be able to reduce the area requirements for individual chips, and thus free up real estate for additional circuitry.
One approach to reducing the area required per chip has been to stack multiple chips vertically in a 3-D arrangement. An example of this approach is the DPS1MS8A3 CMOS SRAM Module by Dense-Pack Microsystems, Inc. In this product, sealed circuit modules are stacked and mounted on PC (printed circuit) boards. A custom fabricated die is required, with input/output (I/O) contacts located across the center of the chip, rather than around its periphery as in the great majority of chip configurations. All of the interconnects between adjacent modules are made by solder along the outer surfaces of the modules, where they can easily be damaged. The modules are formed from high temperature cofired ceramic (HTCC) material, and thus are not compatible with other processes that cannot withstand high temperatures. Also, they are designed for printed circuit board applications only.
Another 3-D circuit package is the SRAM Short Stack.TM. by Irvine Sensors Corporation of Costa Mesa, Calif. In fabricating this package, an expensive lapping process is used to smooth the sides of the individual chips to be stacked, and a metallization is added to each die to extend its contact pads out to the sides of the chip. The chips are then glued together vertically, with exposed and vulnerable interconnects extending along the outside of the stack. A particular disadvantage of this product is that the entire stack fails in the event a single chip within the stack is bad. Once the stack has been assembled, it cannot later be taken apart to replace a bad chip and then reassembled. A single bad chip thus results in the loss of the entire stack.